HARDROC is the very front end chip designed for the readout of the RPC or Micromegas foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider. The very fine granularity of the ILC hadronic calorimeters (1cm2 pads) implies a huge number of electronics channels (4.105 /m3) which is a new feature of “imaging” calorimetry.
Moreover, for compactness, the chips must be embedded inside the detector making crucial the reduction of the power consumption to 10 μWatt per channel. This is achieved using power pulsing, made possible by the ILC bunch pattern (1 ms of acquisition data for 199 ms of dead time).
HARDROC readout is a semi-digital readout with two or three thresholds (2 or 3 bits readout respectively in hardroc1 and hardroc2) which allows both good tracking and coarse energy measurement, and also integrates on chip data storage.
The 64 channels of the 2nd prototype, HARDROC2, are made of:
- A fast low impedance preamplifier with a variable gain over 8 bits per channel
- A variable slow shaper (50-150ns) and Track and Hold to provide a multiplexed analog charge output up to 15pC.
- 3 variable gain fast shapers followed by 3 low offset discriminators to autotrig down to 10 fC up to 10pC. The thresholds are loaded by 3 internal 10 bit- DACs and the 3 discri outputs are sent to a 3 inputs to 2 outputs encoder
- A 128 deep digital memory to store the 2*64 encoded outputs of the 3 discriminators and bunch crossing identification coded over 24 bits counter.
- Power pulsing and integration of a POD (Power On Digital) module for the 5MHz and 40 Mhz clocks management during the readout, to reach 10μW/channel
ASIC name : HARDROC (HAdronic RPC Digital Calorimeter Read-Out Chip)
Current available version : 2B - 3B
Number of channel : 64
Polarity of input signal : negative
Detector read out : RPC, compliant with GEM and micromegas
Equivalent noise charge : 1fC
Gain : 10
Max input signal : 30 pC
|PIN name||PIN type and direction||PIN description|
|IN<63:0>||Analogue input bus (width=64)||Current sensitive analogue inputs to be connected to the detector|
|out_trig<2:0>||3 digital outputs
Provides on 3 pins the outputs of the 3 discriminators of the selected channel using an internal read register. Depending on the Slow control configuration:
|out_Q||Multiplexed analogue output
||Provides the track and hold value of the channel selected by the read register. Can be daisy chained.
|Dout||Open Collector output signal||Memory data, can be daisy chained
Hardroc can be used either for charge measurement or trigger measurement. Each channel can auto-trigger down to 4 fC without any external trigger or machine clock. It integrates a 128 deep digital memory.
There are 3 variable CRRC fast shapers (peaking time ≈ 20-25 ns), followed by 3 discriminators. Trigger efficiency measurements have been performed showing that each channel can trigger down to 4fC which corresponds to the 5σ noise limit.
The power consumption of this 64 channel chip has been measured and is equal to 40 mA (including the 10 mA of the slow channel) which correponds to 132 mW and 2mW/channel . The chip can be power pulsed and the power consumption can be therefore brought down to 10µW/channel with a 0.5% duty cycle as foreseen in ILC experiment.
10 000 HARDROC2B were produced in 2010.
Readout of RPC detectors
Medical imaging applications using the slow channel charge measurement.